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| March 2001 (R) AS7C1025 AS7C31025 5V/3.3V 128Kx8 CMOS SRAM (Revolutionary pinout) Features * AS7C1025 (5V version) * AS7C31025 (3.3V version) * Industrial and commercial temperatures * Organization: 131,072 words x 8 bits * High speed - 12/15/20 ns address access time - 6,7,8 ns output enable access time * Low power consumption: STANDBY - 27.5 mW (AS7C1025) / max CMOS (5V) - 1.8 mW (AS7C31025) / max CMOS (3.3V) * Low power consumption: ACTIVE - 715 mW (AS7C1025) / max @ 12 ns (5V) - 360 mW (AS7C31025) / max @ 12 ns (3.3V) * 2.0V data retention * Easy memory expansion with CE, OE inputs * Center power and ground * TTL/LVTTL-compatible, three-state I/O * JEDEC-standard packages - 32-pin, 300 mil SOJ - 32-pin, 400 mil SOJ - 32-pin TSOP II * ESD protection 2000 volts * Latch-up current 200 mA Logic block diagram VCC GND Input buffer A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O7 Pin arrangement 32-pin TSOP II A0 A1 A2 A3 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 GND VCC I/O5 I/O4 A12 A11 A10 A9 A8 Row decoder 512x256x8 Array (1,048,576) Sense amp I/O0 WE OE CE Column decoder A9 A10 A11 A12 A13 A14 A15 A16 Control circuit 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) A0 A1 A2 A3 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 GND VCC I/O5 I/O4 A12 A11 A10 A9 A8 Selection guide AS7C1025-12 AS7C31025-12 Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current Shaded areas contain advance information. AS7C1025-15 AS7C31025-15 15 4 85 85 5 5 AS7C1025 AS7C31025 AS7C1025 AS7C31025 AS7C1025-20 AS7C31025-20 20 5 80 80 5 5 Unit ns ns mA mA mA mA 12 3 AS7C1025 AS7C31025 AS7C1025 AS7C31025 130 100 5 5 3/23/01; v.1.0 Alliance Semiconductor P. 1 of 9 Copyright (c) Alliance Semiconductor. All rights reserved. AS7C1025 AS7C31025 (R) Functional description The AS7C1025 and AS7C31025 are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 words x 8 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 6,7,8 ns are ideal for high-performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems. When CE is high the devices enter standby mode. The standard AS7C1025 is guaranteed not to exceed 27.5 mW power consumption in standby mode, and typically requires only 5 mW Both devices also offer 2.0V data retention. . A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1025) or 3.3V supply (AS7C31025). The AS7C1025 and AS7C31025 are packaged in common industry standard packages. Absolute maximum ratings Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with VCC applied DC current into outputs (low) Device AS7C1025 AS7C31025 Symbol Vt1 Vt1 Vt2 PD Tstg Tbias IOUT Min -0.50 -0.50 -0.50 - -65 -55 - Max +7.0 +5.0 VCC + 0.5 1.0 +150 +125 20 Unit V V V W o C oC mA NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE H L L L WE X H H L OE X H L X Data High Z High Z DOUT DIN Mode Standby (ISB, ISB1) Output disable (ICC) Read (ICC) Write (ICC) Key: X = Don't Care, L = Low, H = High 3/23/01; v.1.0 Alliance Semiconductor P. 2 of 9 (R) AS7C1025 AS7C31025 Recommended operating conditions Parameter Supply voltage Device AS7C1025 AS7C31025 AS7C1025 Input voltage AS7C31025 commercial industrial Symbol VCC VCC VIH VIH VIL Ambient operating temperature VIL min = -3.0V for pulse width less than tRC/2. Min 4.5 3.0 2.2 2.0 -0.5 0 -40 Nominal 5.0 3.3 - - - - - Max 5.5 3.6 VCC + 0.5 VCC + 0.5 0.8 70 85 Unit V V V V V oC o TA TA C DC operating characteristics (over the operating range)1 -12 Parameter Sym Test conditions Device Min - Max 1 Min - Input leakage | ILI | VCC = Max, VIN = GND to VCC current Output leakage current Operating power supply current | ILO | VCC = Max, CE = VIH, Vout = GND to VCC AS7C1025 ICC CE = VIL, f = fMax, IOUT = 0 mA AS7C31025 AS7C1025 AS7C31025 -15 Max 1 Min - -20 Max 1 Unit A A - - - - - - - - 2.4 1 130 100 50 50 5 5 0.4 - - - - - - - - - 2.4 1 120 85 40 40 5 5 0.4 - - - - - - - - - 2.4 1 110 80 40 40 5 5 0.4 - mA ISB Standby power supply current1 ISB1 Output voltage VOL VOH CE = VIH, f = fMax, fOUT = 0 mA mA V V AS7C1025 CE VCC-0.2V, VIN 0.2V or VIN VCC -0.2V, f = 0, fOUT = 0 AS7C31025 IOL = 8 mA, VCC = Min IOH = -4 mA, VCC = Min Shaded areas contain advance information. Capacitance (f = 1 MHz, Ta = 25 oC, VCC = NOMINAL)2 Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CE, WE, OE I/O Test conditions VIN = 0V VIN = VOUT = 0V Max 5 7 Unit pF pF 3/23/01; v.1.0 Alliance Semiconductor P. 3 of 9 AS7C1025 AS7C31025 (R) Read cycle (over the operating range)3,9 -12 Parameter Read cycle time Address access time Chip enable (CE) access time Output enable (OE) access time Output hold from address change CE Low to output in low Z CE Low to output in high Z OE Low to output in low Z OE High to output in high Z Power up time Power down time Symbol tRC tAA tACE tOE tOH tCLZ tCHZ tOLZ tOHZ tPU tPD Min 12 - - - 3 0 - 0 - 0 - Max - 12 12 6 - - 3 - 3 - 12 Min 15 - - - 3 0 - 0 - 0 - -15 Max - 15 15 7 - - 4 - 4 - 15 Min 20 - - - 3 0 - 0 - 0 - -20 Max - 20 20 8 - - 5 - 5 - 20 Unit ns ns ns ns ns ns ns ns ns ns ns 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 3 3 Notes Key to switching waveforms Rising input Falling input 3,6,7,9 Undefined/don't care Read waveform 1 (address controlled) Address tAA DOUT tRC tOH Data valid Read waveform 2 (CE and OE controlled)3,6,8,9 CE tOE OE DOUT Supply current tPU tACE tCLZ 50% Data valid tPD 50% ICC ISB tOLZ tOHZ tCHZ tRC1 3/23/01; v.1.0 Alliance Semiconductor P. 4 of 9 (R) AS7C1025 AS7C31025 Write cycle (over the operating range)11 -12 Parameter Write cycle time Chip enable (CE) to write end Address setup to write end Address setup time Write pulse width Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end Shaded areas contain advance information. -15 Max - - - - - - - - 5 - Min 15 12 12 0 9 0 8 0 - 3 Max - - - - - - - - 5 - Min 20 12 12 0 12 0 12 0 - 3 -20 Max - - - - - - - - 5 - Unit ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 Notes Symbol tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW Min 12 8 8 0 8 0 6 0 - 3 Write waveform 1 ( WE controlled)10,11 tWC tAW Address tWP WE tAS DIN tWZ DOUT tDW Data valid tOW tDH tAH Write waveform 2 (CE controlled)10,11 tAW Address tAS CE tWP WE tWZ DIN DOUT tDW Data valid tDH tCW tWC tAH 3/23/01; v.1.0 Alliance Semiconductor P. 5 of 9 AS7C1025 AS7C31025 (R) Data retention characteristics (over the operating range)13 Parameter VCC for data retention Data retention current Chip enable to data retention time Operation recovery time Input leakage current Symbol VDR ICCDR tCDR tR | ILI | Test conditions VCC = 2.0V CE VCC - 0.2V VIN VCC - 0.2V or VIN 0.2V Min 2.0 - 0 tRC - Max - 500 - - 1 Unit V A ns ns A Data retention waveform Data retention mode VCC VCC tCDR CE VIH VDR VIH VDR 2.0V VCC tR AC test conditions - - - - 5V output load: see Figure B or Figure C. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. Thevenin equivalent: 168W DOUT +1.728V (5V and 3.3V) +5V 480W +3.0V GND 90% 10% 2 ns 90% 10% DOUT 255W C(14) DOUT 255W +3.3V 320W C(14) Figure A: Input pulse GND Figure B: 5V Output load GND Figure C: 3.3V Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, and C. tCLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured 500mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. NA. 2V data retention applies to commercial temperature operating range only. C=30pF, except all high Z and low Z parameters, where C=5pF. 3/23/01; v.1.0 Alliance Semiconductor P. 6 of 9 (R) AS7C1025 AS7C31025 Typical DC and AC characteristics Normalized supply current ICC, ISB vs. supply voltage VCC Normalized supply current ICC, ISB vs. ambient temperature Ta Normalized ISB1 (log scale) 625 25 5 1 0.2 VCC = VCC(NOMINAL) Normalized supply current ISB1 vs. ambient temperature Ta 1.4 1.2 Normalized ICC, ISB 1.0 0.8 0.6 0.4 0.2 1.4 1.2 Normalized ICC, ISB ICC ICC 1.0 0.8 0.6 0.4 0.2 ISB ISB 0.04 -55 -10 35 80 Ambient temperature (C) 125 0.0 MIN NOMINAL Supply voltage (V) Normalized access time tAA vs. supply voltage VCC MAX 0.0 -55 -10 35 80 125 Ambient temperature (C) Normalized access time tAA vs. ambient temperature Ta 1.5 1.4 Normalized access time 1.3 1.2 1.1 1.0 0.9 0.8 MIN 1.5 1.4 Normalized access time 1.4 1.2 Normalized ICC Normalized supply current ICC vs. cycle frequency 1/tRC, 1/tWC VCC = VCC(NOMINAL) Ta = 25 C Ta = 25 C 1.3 1.2 1.1 1.0 0.9 VCC = VCC(NOMINAL) 1.0 0.8 0.6 0.4 0.2 0.0 NOMINAL Supply voltage (V) Output source current IOH vs. output voltage VOH MAX 0.8 -55 -10 35 80 125 Ambient temperature (C) Output sink current IOL vs. output voltage VOL 0 25 50 75 Cycle frequency (MHz) 100 Typical access time change tAA vs. output capacitive loading 35 30 Change in tAA (ns) VCC = VCC(NOMINAL) 140 Output source current (mA) 120 100 80 60 40 20 0 0 140 Output sink current (mA) 120 100 80 60 40 20 0 VCC 0 VCC = VCC(NOMINAL) Ta = 25 C VCC = VCC(NOMINAL) Ta = 25 C 25 20 15 10 5 0 VCC Output voltage (V) 0 Output voltage (V) 250 500 750 Capacitance (pF) 1000 3/23/01; v.1.0 Alliance Semiconductor P. 7 of 9 AS7C1025 AS7C31025 (R) Package dimensions N N/2+1 32-pin TSOP II Symbol A E1 E 32-pin TSOP II (mil) Min - 0.05 0.3 0.12 20.82 10.03 11.56 1.27 BSC 0.40 0.95 REF. 0 5 0.60 Max 1.2 0.15 0.52 0.21 21.08 10.29 11.96 A1 b C D E1 E 1 D N/2 A ZD Seating plane e L ZD c b A1 L c 32-pin SOJ 300 mil/400 mil e D B E1 E2 A1 b Pin 1 A2 E c Seating Plane A 32-pin SOJ 300 mil Symbol A A1 A2 B b c D E E1 E2 Min 0.025 0.086 0.026 0.014 0.006 0.820 0.250 0.292 0.330 Max 0.145 0.105 0.032 0.020 0.013 0.830 0.275 0.305 0.340 32-pin SOJ 400 mil Min 0.025 0.086 0.026 0.015 0.007 0.820 0.360 0.395 0.435 Max 0.145 0.115 0.032 0.020 0.013 0.830 0.380 0.405 0.445 3/23/01; v.1.0 Alliance Semiconductor P. 8 of 9 (R) AS7C1025 AS7C31025 Ordering codes Package \ Access time Voltage 5V Temperature Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial 12 ns AS7C1025-12TC AS7C1025-12TI AS7C31025-12TC AS7C31025-12TI AS7C1025-12TJC AS7C1025-12TJI AS7C31025-12TJC AS7C31025-12TJI AS7C1025-12JC AS7C1025-12JI AS7C31025-12JC AS7C31025-12JI 15 ns AS7C1025-15TC AS7C1025-15TI AS7C31025-15TC AS7C31025-15TI AS7C1025-15TJC AS7C1025-15TJI AS7C31025-15TJC AS7C31025-15TJI AS7C1025-15JC AS7C1025-15JI AS7C31025-15JC AS7C31025-15JI 20 ns AS7C1025-20TC AS7C1025-20TI AS7C31025-20TC AS7C31025-20TI AS7C1025-20TJC AS7C1025-20TJI AS7C31025-20TJC AS7C31025-20TJI AS7C1025-20JC AS7C1025-20JI AS7C31025-20JC AS7C31025-20JI sTSOP II 3.3V 5V 300-mil SOJ 3.3V 5V 400-mil SOJ 3.3V Part numbering system AS7C SRAM prefix X Blank=5V CMOS 3=3.3V CMOS 1025 Device number -XX Access time X Package: T = TSOP II J = SOJ X Temperature range C = Commercial, 0C to 70C I = Industrial, -40C to 85C 3/23/01; v.1.0 Alliance Semiconductor P. 9 of 9 (c) Copyright Alliance Semiconductor Corporation. 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